1. Technical Field
The present invention relates to a system and method for identifying and manipulating logic analyzer data from multiple clock domains. More particularly, the present invention relates to a system and method for reconstructing debug data that originates in a half frequency domain, or passes through a half frequency domain, in order to process the debug data in a full frequency domain.
2. Description of the Related Art
A device may include multiple frequency domains that operate at different clock rates. Each domain produces debug data on a debug bus at a rate equivalent to its particular clock rate, which proceeds to a centralized internal logic analyzer. When the debug data crosses a boundary from a faster domain to a slower domain, the data undergoes a transformation on the debug bus in order to preserve the data. For example, a 32-bit debug word originating from an N frequency domain spreads into 64 bits of data when crossing to a N/2 frequency domain. In this example, data from even-numbered cycles may be assigned to bits 0:31, and data from odd-numbered cycles may be assigned to bits 32:63. A challenge found is that when the data arrives at the logic analyzer, the “crossed data” is not in a format suitable for the logic analyzer to process.
Complicating matters is the fact that the debug bus must be able to carry debug data from multiple frequency domains in parallel. Meaning, the debug bus may carry full frequency data types, half frequency data types, and crossed data at the same time. A challenge found is processing the debug data in parallel when they include different data types because each type of debug data requires different reconstruction.
What is needed is a system and method to identify an original clock domain of each data segment on the debug bus and reconfigure the data such that the logic analyzer may process the data in a full frequency domain.